1.1.2 CISC, RISC, GPUs and multicore parallel processing Quiz: OCR Computer Science, Unit 1

The 20 questions

1. Which feature is characteristic of a Complex Instruction Set Computer architecture?

   • Variable instruction length
   • Single cycle execution
   • Heavily pipelined
   • Fixed instruction length

2. How many clock cycles do most instructions take to execute in a RISC processor?

   • Multiple clock cycles
   • Zero clock cycles
   • One clock cycle
   • Variable clock cycles

3. Why are compilers generally more complex for RISC processors than CISC processors?

   • Variable length instructions
   • Fewer registers available
   • Hardware instruction decoding
   • More instructions needed

4. Which processor type relies on complex built-in hardware to decode compound instructions?

   • GPU
   • CISC
   • RISC
   • Parallel core

5. How does register availability in RISC processors compare to CISC processors?

   • RISC has fewer
   • RISC has none
   • Both are equal
   • RISC has more

6. What structural feature allows GPUs to process graphics data extremely quickly?

   • Thousands of cores
   • Large L3 cache
   • Complex branch prediction
   • High clock speed

7. Which task is most suitable for offloading to a GPU rather than a CPU?

   • Matrix multiplication
   • Compiling source code
   • Single-threaded calculations
   • OS task scheduling

8. Why is instruction pipelining easier to implement in RISC processors than CISC?

   • Fixed instruction size
   • Variable execution time
   • Larger memory footprint
   • Microcode execution

9. Which description best defines the physical structure of a contemporary multicore processor?

   • Multiple physical cores
   • Multiple separate CPUs
   • Single processing unit
   • Virtualised core software

10. What limits the speedup gained when adding more cores to a multicore system?

    • Increased cache size
    • High RAM capacity
    • Fixed instruction length
    • Sequential software sections

11. Why are RISC processors predominantly used in smartphone devices?

    • Complex instructions
    • Microcode decoding
    • Lower power consumption
    • Higher thermal output

12. Which parallel processing classification describes a GPU applying one operation across multiple data sets?

    • SISD
    • SIMD
    • MIMD
    • MISD

13. Which architecture executes different instructions on different datasets simultaneously across multiple cores?

    • SIMD
    • SISD
    • MIMD
    • MISD

14. Compared to a CPU core, how is an individual GPU core designed?

    • Identical in structure
    • Simpler and slower
    • Larger cache size
    • Faster and complex

15. What internal feature do CISC processors use to break down complex instructions into simpler micro-operations?

    • Registers
    • Accelerators
    • Microcode
    • Compilers

16. What primary hardware bottleneck occurs when multiple cores attempt to access main memory simultaneously?

    • Bus contention
    • Pipelining stall
    • Register overflow
    • Cache failure

17. What mechanism ensures that all cores in a multicore system see identical data in cache?

    • Cache coherency
    • Bus pipelining
    • Branch prediction
    • Memory swapping

18. How do the number of addressing modes in CISC compare to those in RISC?

    • RISC has infinite
    • CISC has more
    • CISC has fewer
    • Both are identical

19. What distinguishes a distributed system from a standard multicore parallel system?

    • Unified system cache
    • Independent memory spaces
    • Shared clock speed
    • Single CPU motherboard

20. Which instruction architecture restriction forces RISC processors to perform operations using only register data?

    • Direct-mapped architecture
    • Load/store architecture
    • Memory-register architecture
    • Accumulator architecture

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