1.1.1b Fetch-decode-execute, CPU performance, pipelining and architectures Quiz: OCR Computer Science, Unit 1

The 20 questions

1. Which bus transfers the actual data or instruction between RAM and the MDR?

   • System bus
   • Data bus
   • Control bus
   • Address bus

2. How does increasing CPU cache size improve overall processing performance?

   • Increases clock speed
   • Eliminates heat output
   • Adds extra cores
   • Reduces RAM accesses

3. Which unit measures the execution clock speed of contemporary computer processors?

   • Gigabytes
   • Megabits
   • Gigahertz
   • Teraflops

4. Why might doubling CPU cores not double performance for all computer programs?

   • Sequential code limitations
   • RAM speed doubles
   • Cache becomes full
   • Buses overheat instantly

5. What is the primary purpose of instruction pipelining in a modern CPU?

   • Increase instruction throughput
   • Eliminate cache memory
   • Decrease RAM capacity
   • Reduce clock speed

6. Which condition causes a pipeline hazard and forces a CPU pipeline stall?

   • Incrementing the counter
   • Branching instruction
   • Reading from cache
   • Adding two registers

7. Where is pure Harvard architecture most commonly used in contemporary computing?

   • Standard office laptops
   • Mainframe web servers
   • General-purpose desktop PCs
   • Digital Signal Processors

8. What is arithmetic pipelining specifically used for in modern processors?

   • Decoding instructions faster
   • Sequencing memory fetches
   • Stalling pipeline cycles
   • Overlapping arithmetic operations

9. Which CPU component manages timing and generates control signals during execution?

   • Control Unit
   • Arithmetic Logic Unit
   • Accumulator
   • Memory Data Register

10. What type of data is temporarily held inside the CPU accumulator register?

    • System interrupt flags
    • Next instruction address
    • ALU calculation results
    • Main memory addresses

11. Why can overclocking a processor cause system instability and operational failure?

    • RAM capacity decreases
    • Excessive heat generation
    • Data bus shrinks
    • Instruction set changes

12. Modified Harvard architecture differs from pure Harvard by sharing which system component?

    • Data bus only
    • ALU registers
    • Main memory space
    • Address bus only

13. What action does a CPU take when flushing an instruction pipeline?

    • Caching branch results
    • Executing all instructions
    • Discarding incorrect instructions
    • Locking register sets

14. What defines the primary feature of a traditional Von Neumann processor architecture?

    • Dedicated instruction cache
    • Separate memory units
    • Shared memory space
    • Multiple CPU cores

15. Which property correctly describes the direction of signal transmission along the CPU address bus?

    • Unidirectional
    • Duplex
    • Bidirectional
    • Omnidirectional

16. What architectural feature allows a Harvard CPU to fetch instructions and read data simultaneously?

    • Unified L3 cache
    • Shared system bus
    • Variable clock speeds
    • Separate memory buses

17. What determines the maximum amount of RAM a processor can directly address?

    • Cache size
    • Data bus width
    • Clock speed
    • Address bus width

18. Which part of a machine code instruction specifies the operation to be performed?

    • Operand
    • Addressing mode
    • Opcode
    • Immediate value

19. What determines the maximum number of bits a CPU can transfer simultaneously in one cycle?

    • Data bus width
    • Cache line size
    • Address bus width
    • Clock frequency

20. Which pipeline stage interprets the instruction opcode and retrieves any required register values?

    • Decode stage
    • Fetch stage
    • Writeback stage
    • Execute stage

Related quizzes

• Processor components: ALU, control unit, registers and buses Quiz · 1.1.1a · 20 questions
• CISC, RISC, GPUs and multicore parallel processing Quiz · 1.1.2 · 20 questions
• Input, output and storage devices applied to problems Quiz · 1.1.3a · 20 questions
• Magnetic, flash and optical storage, RAM, ROM and virtual storage Quiz · 1.1.3b · 20 questions
• Operating systems and memory management Quiz · 1.2.1a · 20 questions
• Compression, encryption and hashing Quiz · 1.3.1 · 20 questions
• Primitive data types and binary number representation Quiz · 1.4.1a · 20 questions
• Data Protection Act 1998 and Computer Misuse Act 1990 Quiz · 1.5.1a · 20 questions
• The nature and need for abstraction and abstract models Quiz · 2.1.1 · 20 questions
• Programming constructs, recursion and variable scope Quiz · 2.2.1a · 20 questions